Structural and dielectric properties of giant dielectric Na1/2Sm1/2Cu3Ti4O12 ceramics prepared by reactive sintering methods
Mahfoz Kotb H1, 2, †
Department of Physics, College of Science, King Faisal University, Al-Hassa 31982, Saudi Arabia
Department of Physics, Faculty of Science, Assiut University, Assiut 71516, Egypt

 

† Corresponding author. E-mail: hkotb@kfu.edu.sa

Abstract

Na0.5Sm0.5Cu3Ti4O12 (NSCTO) ceramics have been prepared by reactive sintering of amorphous powder. Spark plasma sintering (SPS) for 10 min at 1025 °C and conventional sintering (CS) for 10 h at 1090 °C have been employed. X-ray diffraction measurements confirmed the pure CCTO-like phase for SPS and CS NSCTO ceramics. The SPS ceramic showed an average grain size of 500 nm, which is much smaller than that of the CS ( ) sample. The impedance spectroscopy measurements revealed an electrically inhomogeneous structure in the prepared ceramics. While the resistivities of grains of both ceramic samples were in the same order of magnitude, the resistivity of grain-boundaries of the CS ceramic was three orders of magnitude greater than that of the SPS ceramic. Both of the samples showed giant dielectric constant ( ) over wide ranges of temperatures and frequencies. Nevertheless, the room-temperature dielectric loss of the SPS NSCTO (3.2 at 1.1 kHz) ceramic sample was higher than that of the CS NSCTO (0.08 at 1.1 kHz) ceramic sample due to the reduced grain-boundary resistivity of the former. Two dielectric relaxations were detected for each sample and attributed to the relaxations in grains and grain-boundaries. The dielectric behavior of the SPS and CS NSCTO ceramics could be interpreted in terms of the internal barrier layer capacitor (IBLC) model.

1. Introduction

Materials with giant dielectric constant (GDC) (103–105) are of great importance for many technological applications such as multilayer ceramic capacitors and memory devices.[1] Hopefully, these materials will replace silicon oxide as the gate insulator which would contribute to further miniaturization of metal–oxide–semiconductor (MOS) electronic devices. Among the promising GDC candidates for such applications is the titanates family, which includes a variety of ceramic systems, e.g., [A]Cu3Ti4O12 (A = Ca, Na, Cd, Sr, Y2/3, Bi2/3, and Ln2/3, Ln: Sm, Ce, Er, Gd, Pr, Nd, Ho, Tb, and Tm)[24] and [Na1/2 B1/2]Cu3Ti4O12 (B=Y, Bi, La, Sm).[59] The dielectric properties of these materials showed a considerable dependency on the synthesis and post-synthesis processing conditions. CaCu3Ti4O12 (CCTO), for example, has been reported to have a dielectric constant ( ) in the range –105 and dielectric loss ( ) ∼0.014–1 at 1 kHz and room temperature,[2,1016] depending on the fabrication methods and conditions. Most of studies on the GDC ceramics used the standard solid state reaction technique which is based on mixing the appropriate amounts of the elemental oxides followed by multiple steps of calcination and sintering at high temperature for many hours to obtain the dense, pure phase ceramics.[2,3,7,9] However, recent reports demonstrated successful combinations of new synthesis techniques, e.g., sol–gel,[17] autocombustion,[18] and sintering techniques, e.g., hot pressing,[12] microwave[19] and spark plasma sintering (SPS)[5,20] instead of the standard solid state reaction. Among the objectives of modifying the preparation method is to render the process simpler, to reduce the thermal budget, and possibly to improve the dielectric properties. Thus, researches on new GDC materials and/or simplified fabrication processes are still welcomed. One of the promising GDC materials is Na0.5Sm0.5Cu3Ti4O12 (NSCTO). Somphan et al.[9] reported giant dielectric constant ( ) and very low dielectric loss ( ) for NSCTO prepared by the standard solid state reaction method. These results are very competitive to those reported for CCTO. The used process in Ref. [9] includes mixing the starting materials using 24 h ball-milling, calcination of the prepared powder at 1050 °C for 20 h, followed by sintering at 1100–1110 °C for 10 h. In the present work, we explore the structural and electrical properties of Na0.5Sm0.5Cu3Ti4O12 ceramic system prepared by a simple reactive sintering. The process is based on one-step sintering of the mixed starting materials without any calcination steps. Two sintering techniques are used: conventional sintering (CS) inside a tubular furnace in air and spark plasma sintering (SPS) under vacuum. The different structural and electrical properties of the prepared ceramics are compared and discussed in order to reveal the origin of giant dielectric properties and electrical behavior of the prepared ceramic samples.

2. Experiment

In the present study, the powder was prepared by high energy mechanochemical milling of stoichiometric amounts of Na2CO3 (99.99%, Aldrich), Sm2O3 (99.99%, Aldrich), CuO (99.995%, Aldrich), and TiO2 (99.9%, Aldrich). Fritsch P-7 premium line machine has been used for 10 h with a rotation speed of 500 rpm using a 45 ml tungsten carbide pot and tungsten carbide balls. The dense ceramics of Na1/2Sm1/2Cu3Ti4O12 were obtained by using two sintering techniques: (i) conventional sintering (CS), where the pelletized powder, 12 mm in diameter and 1.5 mm in thickness, was sintered in air at 1090 °C for 10 h in an electric tubular furnace; (ii) spark plasma sintering using the SPS 4–10 system (Thermal Technology LLC). SPS was carried out under vacuum at 1025 °C for 10 min with a heating rate of 200 °C/min. The powder was confined in a 12 mm graphite die under 60 MPa pressure and a dwelling time of 5 min followed by rapid cooling. The prepared ceramics are abbreviated in the following as SPS025 and CS090, respectively. The measured relative densities of the sintered samples were above 95% of the theoretical density (4.9 g/cm3).[11] For morphological and structural characterization, field emission scanning electron microscope (FE-SEM, Joel, SM7600F) equipped with energy-dispersive x-ray (EDX) and powder x-ray diffraction (XRD) equipments were used. XRD was performed using a Stoe Stadi-P image plate (IP, Stoe and Cie GmbH, Darmstadt, Germany), with monochromated Cu 1 radiation (λ = 1.5406 Å). Impedance spectroscopy (IS) measurements were performed over the 1 Hz–20 MHz frequency range by the turnkey concept 50 system from Novocontrol. IS experiments were realized in dry nitrogen atmosphere in the 120–400 K temperature range, where the temperature was controlled by the Quatro Cryosystem.

3. Results and discussion
3.1. Structure and microstructure analysis

Figure 1 shows the XRD patterns for the as-prepared powder, CS090 and SPS025 ceramics of NSCTO. On one hand, the as-prepared powder is almost amorphous with no evidence on the formation of the CCTO-cubic like phase. Few tiny peaks could be identified in the XRD pattern of the powder and attributed to unreacted TiO according to JCPDS card No. 08-8117. On the other hand, the XRD patterns of the sintered ceramics confirm the CCTO-like crystalline phase where all the main peaks could be assigned according to JCPDS card No. 75-2188 of CCTO. A tiny peak located at 36.528° is found in the XRD pattern of the SPS025 ceramic and attributed to Cu2O according to the JCPDS card No. 78-2076. The lattice parameter is calculated from the XRD patterns using UnitCellWin software and found to be 7.396 Å and 7.399 Å for the SPS025 and CS090 ceramics, respectively. These values are in accordance with the previous studies.[2,9]

Fig. 1. Room temperature XRD patterns of the as-prepared powder, SPS025 and CS090 Na1/2Sm1/2Cu3Ti4O12 ceramics.

FE-SEM images of the fractured surfaces of the sintered ceramics are revealed in Fig. 2. Both ceramics show a clear grain/grain boundary structure. Moreover, the SPS025 ceramic shows an average grain size of ∼500 nm, which is much smaller than that of the CS090 sample ( ).

Fig. 2. FE-SEM micrographs of (a) SPS025 and (b) CS090 Na1/2Sm1/2Cu3Ti4O12 ceramic samples.

It is worthy to note that the grain sizes of the current samples are much smaller than those reported for the conventionally ( )[15,21] and spark plasma ( )[22] sintered CCTO ceramics. Figure 3 shows the elemental analysis in the grain and grain-boundary regions of the SPS025 and CS090 ceramics and the quantitative results are given in Table 1. It is seen that while the elements compositions in the grains and grain-boundary of SPS025 are nearly stoichiometric, the grain-boundary region of the CS090 ceramic is rich in Cu as compared with grains. It is known that the penetration depth of EDX is in the range of , which is much larger than the width of the grain-boundary. Consequently, the obtained EDX analysis in grain-boundary represents the mixture of the spectra of grains and grain-boundaries. Therefore, we think that the real Cu-content in the grain-boundaries is higher than the value given in Table 1, more particularly in the case of the SPS025 sample.

Fig. 3. EDX spectra inside the (a) grain and (b) grain-boundary of SPS025, (c) grain and (d) grain-boundary of CS090.
Table 1.

Elemental analysis of the grain and grain-boundary regions for SPS025 and CS090 Na1/2Sm1/2Cu3Ti4O12 ceramic samples.

.
3.2. Impedance spectroscopy analysis

The complex impedance (CI) plots at different temperatures for the SPS025 and CS090 ceramics are given in Figs. 4 and 5, respectively. The CI plots for CS090 show two semicircular arcs for all measuring temperatures. Meanwhile, these plots for SPS025 are found to be composed of two semicircular arcs at low temperatures ( ). At higher temperatures, a third arc appears at very low frequencies. It is worthy to remind that in the CI plots, in addition to the semicircle at high frequencies which is originated from the bulk response, additional semicircles might appear at lower frequencies due to the internal boundaries, e.g., domain-boundaries, grain-boundaries, and/or the sample/electrode interface effect.[23] Based on Refs. [24] and [25], the electrode effect is suggested to interfere only in ceramics with low grain boundary resistivity of few at room temperature. Considering the low resistivity of the SPS025 ceramic as seen from Fig. 4, it is thought that the semicircular arc at very low frequencies of this sample is due to the electrode effect. This speculation could be further verified using the modulus spectroscopy analysis as it will be discussed in the next sections. Besides, all the semicircular arcs of the complex impedance for the current samples are found to be depressed, which indicates a non-Debye relaxation with distributed relaxation time.[6] Possible causes of the non-ideal Debye behavior are the heterogeneity of the barriers, porosity, or electrode roughness.[26,27] Moreover, the radii of the arcs decrease with the increase of measuring temperature, suggesting a semiconducting behavior. Using ZsimpWin 3.10 software, the measured data of the complex impedance can be well fitted using an equivalent circuit of two elements ( and connected in series. A third element is necessary for the fitting of SPS025 at high temperatures, possibly due to the electrode effect. Here R, C, and Q represent the resistance, capacitance, and constant phase element (CPE) of the electrically active component of the sample, i.e., grains, internal-boundaries, and electrode effect. CPE is widely used to account for the depressed complex impedance arcs of imperfect dielectrics.[28]

Fig. 4. Impedance complex plane plots for the SPS025 Na1/2Sm1/2Cu3Ti4O12 ceramic in the (a) low temperatures and (b) high temperatures ranges. The insets show an expanded view of the high frequency region and the corresponding equivalent circuit.
Fig. 5. Impedance complex plane plots at selected temperatures for the CS090 Na1/2Sm1/2Cu3Ti4O12 ceramic. The insets show an expanded view of the high frequency region and the used equivalent circuit.

The capacitance of CPE is given by , where n is a parameter ranging from n = 0 for purely resistance behavior to n = 1 for purely capacitive behavior. As shown in Figs. 4 and 5, the fitting results (solid lines) are in close agreement with the measured data (symbols). In this way the resistivity of the grain and grain-boundary of the studied ceramics could be extracted at each temperature. The obtained resistivity values from the fitted impedance curves at room temperature for SPS025 and CS090 are summarized in Table 2. While the resistivities of grains for both samples are comparable, the resistivity of grain-boundaries of CS090 is three orders of magnitude greater than that of SPS025. Moreover, the resistivity of grain-boundaries is 2 and 5 orders of magnitude greater than the resistivity of grains in the SPS025 and CS090 ceramics, respectively. These results suggest that the current samples have an electrically inhomogeneous microstructure comparable to that of CCTO and its related ceramics,[8,22] in form of insulating grain-boundaries surrounding semiconductor grains. Several models have been proposed for the interpretation concerning the formation of semiconductor grains and insulator grain boundaries in CCTO and its related materials. Some authors attributed the semiconductivity of grains in these ceramics to the mixed valence Ti3+/Ti4+ and Cu1+/Cu2+ conduction.[29,30] Possibly, the mechanism for the formation of the multivalent ions during the high temperature sintering can be expressed using the Kroger–Vink notation of defects as follows:

The released electrons might be captured by Ti+4 and Cu+2, resulting in the formation of Ti+3 and Cu+ ions. Thus, hopping of electrons between these ions enhances the conductivity of grains in these ceramics. The presence of the multivalent ions Cu+2/Cu+ and Ti+4/Ti+3 in CCTO related ceramics have been practically evidenced.[31] On cooling of the sample, re-oxidation takes place more particularly at the grain-boundaries, which results in much more insulating grain-boundaries as compared to the grains. More recently, Costa et al.[32] showed that the grains of CCTO ceramics are highly resistive when the maximum processing temperature is lower than 700 °C. For higher processing temperatures, a semiconductor grain-core starts to grow out of the electrically resistive phase. For sintering temperature in the range of 1000–1100 °C, the electrically resistive phase exists only at the grain/grain-boundary region, which surrounds the semiconductor grain. It is worthy to note that the insulating gain-boundary phase has been evidenced to be Cu-rich,[33] which is consistent with the EDX results given in Table 1 for the current study. Figure 6 depicts the temperature dependencies of conductivities (σ) of grains and grain-boundaries for SPS025 and CS090. The good linear fit of with 1/T is in agreement with the nearest neighbor hopping (NNH) relationship
where is the pre-exponential factor, kB is the Boltzmann constant, and is the activation energy for conduction.

Fig. 6. The Arrhenius plots of grain and grain boundary conductivity for SPS025 and CS090 ceramics.
Table 2.

The resistivity of grain (Rg), grain-boundary (Rgb) and the activation energy for conduction ( ) and for relaxation process (ER) in grain and grain boundary of NSCTO ceramics.

.

The calculated values of the activation energy for conduction in grains and grain-boundaries are added on Fig. 6 and given in Table 2. On one hand, the values of show little differences for SPS025 (0.128 eV) and CS090 (0.139 eV) samples. On the other hand, for both samples, the temperature dependence of the grain-boundaries conductivity exhibits two linear regions with different activation energies. The breaking temperature is 260 K and 290 K for SPS025 and CS090, respectively. The values of for the ceramic CS090 are found to be 0.348 eV and 0.581 eV in the low and high temperature regions, respectively. Lower values of 0.311 eV and 0.396 eV are obtained for SPS025 in the low and high temperature regions, respectively. The obtained values of agree well with the values reported for conduction in grains and grain-boundaries of CCTO and CCTO-like ceramic systems prepared by different techniques.[5,13,15] It is worthy to note that the lower activation energy for conduction inside the grain and grain-boundaries of SPS ceramics compared to that of CS ceramics was previously reported for Na1/2Y1/2Cu3Ti4O12[5] and CCTO.[34] This difference is closely related to the resistivity difference between these ceramics.

3.3. Conductivity analysis

The frequency dependence of at different measuring temperatures is shown in Fig. 7. A plateau is observed in the low frequency range, followed by a dispersion region at higher frequencies. The low frequency plateau of ac conductivity at high temperature is nearly equal to the dc conductivity of the sample. With increasing temperature, the conductivity increases and becomes more frequency independent in the low frequencies and the dispersion region shifts towards higher frequencies.

Fig. 7. The frequency dependence of at different temperatures for (a) SPS025 and (b) CS090 Na1/2Sm1/2Cu3Ti4O12 ceramics, insets show the Arrhenius plots of .

This behavior of the ac conductivity dependence on frequency and temperature is compatible with Jonscherʼs power law[35]

where is the dc conductivity and s ( ) is a constant. The insets of Fig. 7 show the plot of the inverse temperature variation of for each sample. The obtained activation energies for dc conduction in the low and high temperature ranges are 0.317 eV and 0.376 eV, respectively, for the SPS025 ceramic, while the activation energy for dc conduction in the high temperature range is 0.597 eV for the CS090 ceramic. These values are very close to the activation energies of conduction in grain-boundaries that were obtained from complex impedance analysis (Table 2). These results suggest that the dc conductivity of the present samples is dominated by the grain-boundaries. In fact, the role of grain-boundary is dominant at low frequencies and high temperatures. Under these conditions, the electrical conduction takes place by long range hopping where the motion of charge carriers is not localized within the grains due to the low frequency of the applied electric field and the increased mobility of the charge carriers. Therefore, the grain boundary is expected to affect the motion of charge carriers, which justifies the higher value of in the high temperature range for the CS090 ceramic (0.581 eV) as compared to ceramic SPS025 (0.396 eV).

3.4. Dielectric properties analysis

Figure 8 reveals the frequency dependences of and at room temperature for CS090 and SPS025. Both of the samples exhibit giant dielectric constant over wide ranges of frequencies and temperatures. The values of and at 295 K and 1.1 kHz are 8.93×103 and 3.22 for the SPS025 sample, while they are 4.28×103 and 0.08 for the CS090 sample. Somphan et al. reported and of ∼7–8.4×103 and 0.041–0.03, respectively, at 293 K and 1.1 kHz for the NSCTO ceramics prepared by the standard solid state reaction method,[9] which are comparable to our findings. The higher values of and of the SPS025 ceramic are thought to be due to its higher conductivity as discussed in the previous section. One of the most accepted models for explaining the giant dielectric constant of GDC materials is the internal barrier layer capacitance (IBLC) model.[36] As suggested by Sinclair et al.,[36] this model is suitable for polycrystalline ceramics with electrically inhomogeneous structure in form of semiconductor grains separated by insulating grain boundaries. Therefore, under the effect of an applied alternating voltage, charges displace from the less resistive grains and pile up at the grain boundaries, thus causing the Maxwell–Wagner (M–W) interfacial polarization effect. At high frequencies, decreases as a result of the reduction of the interfacial polarization effect due to the inability of charge carriers to follow up the variation of the applied alternating electric field. Considering the electrically heterogeneous structure revealed by the complex impedance analysis, the giant dielectric constant behavior of the current NSCTO samples can be explained by the IBLC model.

Fig. 8. Frequency dependence of and at 295 K for SPS025 and CS090 Na1/2Sm1/2Cu3Ti4O12 ceramics.

The evolution of the spectra of and with temperature is given in Figs. 9(a) and 8(b) for the samples CS090 and SPS025, respectively. All samples show two step-like decreases in the dielectric constant spectra within the covered temperature and frequency ranges. At low temperatures ( ), the first step-like decrease is seen in the high frequency range (105–107 Hz). At higher temperatures, a second step appears at low frequencies ( ). Two clear broad peaks (R1 and R2) are observed in the spectra of tanδ of the sample SPS025 corresponding to the two step-like decreases in the spectra of . These results suggest that there exist at least two dielectric relaxations processes in the SPS025 and CS090 ceramics.

Fig. 9. Frequency dependence of and at selected temperatures for (a) SPS025 and (b) CS090 Na1/2Sm1/2Cu3Ti4O12 ceramics.

To have more information on the dielectric relaxation behavior, we analyze the spectra of the imaginary part of the electric modulus , where is the complex permittivity. A major advantage for using the spectroscopic plots of is the suppression of the electrode polarization effect.[37] Figure 10 shows the spectra of the imaginary part of electric modulus at selected temperatures for the current samples. At a given temperature, the spectrum of for each sample contains only two asymmetric electrical relaxation peaks falling in two different frequency regions. These peaks will be referred to as HFR and LFR for the high and the low frequency peaks, respectively. It is worthy to note from Fig. 10 that the HFR peaks of the SPS025 and CS090 samples have some common features. In particular, these peaks appear in the same low temperature range (120–180 K). At certain temperature, they have almost the same amplitude and peak frequency fmax irrespective of the sintering technique. These observations support that the HFR relaxation peaks are of intrinsic origin. As compared to the HFR peaks, the low frequency relaxation peaks appear at higher temperatures. Furthermore, the observed HFR and LFR peaks for all the samples are shown to be thermally activated where they shift towards higher frequencies with increasing temperature.

Fig. 10. Frequency dependence of for (a) SPS025 and (b) CS090 Na1/2Sm1/2Cu3Ti4O12 ceramics at some selected temperatures. The insets show an expanded view of the low frequency region.

Based on the results of the complex impedance analysis, the IBLC model, and the fact that the peak height of is inversely proportional to the associated capacitance,[32,38] we ascribe the modulus relaxation peaks HFR and LFR to the effects of the grain and grain-boundaries, respectively, on the conductivity relaxation of the sample.

The characteristic frequency fmax is related to the mean value of the conductivity relaxation time τ as . As shown in Fig. 11, the temperature dependency of fmax fits well with the Arrhenius law

where f0 is the pre-exponential term and ER is the activation energy for conductivity relaxation.

Fig. 11. The log(fp) versus 1000/T for the SPS025 and CS090 Na1/2Sm1/2Cu3Ti4O12 ceramics.

As indicated in Table 2, the activation energies of the high frequency relaxation peaks EHFR are 0.091 eV and 0.095 eV for SPS025 and CS090, respectively. These values are in good agreement with the widely reported value of ∼0.1 eV for the intrinsic relaxation in grains[39,40] and comparable with the activation energy for hopping of electrons between Ti3+ and Ti4+ ions (0.13 eV).[41] Therefore, the HFR relaxation peaks are thought to be linked with the structure defects inside the grains such as oxygen vacancies and the multivalent ions.

The activation energies for the low frequency relaxation peaks ELFR are found to be 0.350 eV and 0.541 eV for SPS025 and CS090, respectively, which are consistent with the literature values for the M–W relaxation associated with grain-boundaries of CCTO-like ceramics.[5,42] Besides, one can see from Table 2 that the activation energies obtained in the modulus formalism are close to those obtained in the impedance formalism of the current samples.

4. Conclusion

The microstructural and electrical properties of Na0.5Sm0.5Cu3Ti4O12 (NSCTO) ceramics prepared by reactive sintering of amorphous powder were investigated. Reactive spark plasma SPS sintering has resulted in ceramics with much smaller grain size (∼500 nm) than that of reactive conventional sintering CS ( ). The impedance spectroscopy measurements revealed an electrically inhomogeneous structure for the prepared ceramics. Both ceramic samples showed pure CCTO-like phase, giant dielectric constant ( ) over wide ranges of temperatures and frequencies. Nevertheless, the dielectric loss of the SPS NSCTO ceramic at room temperature was found to be much higher than that of the CS ceramic due to the higher conductivity of grain-boundaries of the former. Investigating the relaxation behaviors by studying the modulus spectra revealed two dielectric relaxations for each sample. These relaxations were attributed to the relaxations in grain and grain-boundaries of the studied ceramics. The dielectric behaviors of the SPS and CS NSCTO ceramics were consistent with the internal barrier layer capacitor model. The overall results of the current study approved the possibility of preparing dense, pure phase and giant dielectric constant NSCTO ceramics using simplified reactive sintering (CS and SPS) based processes. The reactive SPS has the additional advantage of being very short in time. Though the comparatively high of the prepared ceramics using reactive SPS, we think it can be further reduced via the optimization of the SPS process parameters such as the plateau temperature, the dwell time, and the atmosphere during the sintering.

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